1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to repeater structures implemented in integrated circuits.
2. Description of Related Art
Integrated circuits are widely manufactured on semiconductor chips to process signals. Semiconductor chips are typically formed of various layers that contain a multitude of circuit components and interconnecting structures that route the signals between the various circuit components on a layer and between layers. It can be appreciated by those of skill in the art that the terms chip, integrated circuit and I.C. can have the same meaning.
One structure used for routing signals between circuit components is a wire bus. Wire buses are typically formed on metal layers of a semiconductor chip and are composed of individual signal wires. To aid in maintaining the signal integrity of a signal carried on a signal wire, shielding wires are often routed to each side of a signal wire to prevent interference from other signals or charges. As there are only a limited number of layers on each semiconductor chip, it is important that circuit designers make the most efficient use of the available routing space on each metal layer.
When the integrated circuit design and mask topology is created for a metal layer, the signal wires of a wire bus are conventionally designed to a particular wire pitch defined by a specified fabrication process or design parameter. In this instance, the term wire pitch refers to a distance between center lines of two signal wires. Thus, the wire pitch establishes the spacing of adjacent signal wires of the bus for a given metal layer. A minimum wire pitch is typically used in designing the wire bus topology so that as much of the metal layer as possible is utilized for routing signals and wasted space is minimized. The term minimum wire pitch refers to the minimum distance between the center lines of two signal wires on the same metal layer required to prevent a short and/or interference.
Relatively speaking, wire buses often span long distances on a semiconductor to interconnect the various circuit components. If the signal wires become too long, a signal conducted on the signal wire can degrade and slow. If the signal degrades too much, the performance of the circuit can be impaired, for example, by the timing of the signal to a receiving circuit drifting out of specification or the signal amplitude degrading to an unusable level. Thus, repeaters that amplify the signal are often placed on the individual signal wires of the bus to reduce signal degradation and prevent reduced performance. Some examples of repeater structures are inverters, buffers, flip-flops and logic gates. Similar to signal wires, repeaters typically contain some conductive metal, and thus, repeaters are placed in conformance with the minimum wire pitch constraints of a design so that a short does not occur.
FIG. 1 illustrates a generalized integrated circuit wire bus in the prior art interconnecting two circuits on a metal layer of an integrated circuit. On metal layer 110, circuit components 112 and 114 are interconnected by a wire bus 116 composed of individual signal wires 118 separated by a wire pitch 130, such as a minimum wire pitch. In the illustration, shielding wires 120 are also present to each side of an individual signal wire 118.
If the length of wire bus 116 is such that the parasitic resistance, capacitance and inductance, or other physical properties associated with wire bus 116, causes signal degradation to occur, repeaters can be introduced into the wire bus to amplify the signals. One prior art technique used to introduce repeaters on an integrated circuit wire bus is to place a repeater structure on each signal wire of the bus.
FIG. 2 illustrates a generalized integrated circuit wire bus in the prior art in which individual repeaters are located on each signal wire in the bus. In the illustration, circuit components 212 and 214 are interconnected by a integrated circuit wire bus in which individual repeaters 222 are placed on each signal wire 218 of the wire bus and coupled with the signal wire 218 at points 218A and 218B. Shielding wires 220 typically terminate at the boundaries of repeaters 222.
Currently, conventional repeaters are typically much larger than the minimum wire pitch constraints of an integrated circuit bus. For example, a minimum wire pitch constraint on signal wires of a bus can be 0.18 microns, but a typical repeater can be approximately 5.0 microns by 5.0 microns. Thus, to accommodate the repeaters 222, some or all of individual signal wires 218 of the bus are vertically spread out to maintain at least the minimum wire pitch 230 between signal wires 218 and a minimum spacing 228 between repeaters 222 as required by the manufacturing process. Where spacing 228 refers to a dimension between repeaters.
To spread out the signal wires 218 and the shielding wires 220, one or more xe2x80x9cwire jogsxe2x80x9d 224 are inserted. In the presently illustrated prior art technique, the vertical and horizontal segments of the signal wires 218 and shielding wires 220 used to create wire jogs 224 are located on the same metal layer. However, no horizontal routing on this metal layer can pass through the area above or below circuit component 212 and 214 where the horizontal routing is blocked by the vertical segment of the wire jog as this would create a short. For example, as illustrated in FIG. 2, a horizontal routing (shown in dashed lines) would not be allowed as it would create a short where it is blocked by the vertical segments of the wire jogs.
As illustrated, this technique increases the width of the overall bus and results in increased use of area on the metal layer by the bus. Put another way, this technique increases the footprint of the bus over that of the bus without the repeaters. Further, the increased footprint is contributed to, but not limited to, having to maintain the minimum spacing between the repeaters as required by the manufacturing process.
Routing of the signal wires and shielding wires to accommodate the repeater circuits and the placement of wire jogs in each signal wire of the bus requires tool and/or designer intervention. Thus, using this technique to insert repeaters into a bus increases the complexity of the integrated circuit design, increases expenditure of tool work and/or design time, increases the footprint of the bus on the metal layer and, typically, results in higher production costs.
Another prior art technique, uses different metal layers on which to route the vertical segments and horizontal segments of the wires and interconnects the vertical and horizontal segments using vias between the metal layers. FIG. 3 illustrates a generalized view of an integrated circuit wire bus in the prior art having vertical wire segments routed on a metal layer different from that on which the horizontal wire segments are routed.
Conventionally, adjacent metal layers are routed orthogonal to each other by most semiconductor manufacturing processes and integrated circuit design teams. In FIG. 3, the horizontal segments of the signal and shielding wires are routed on a first metal layer 310, designated as M1, and the vertical segments are routed on a different, second metal layer, designated M2, not shown. The vertical and horizontal segments of the wires 318 and 320 are interconnected using vias (not shown) between the metal layers. This prior art technique solves the problem of the blocked routing on the original metal layer, but in turn reduces the amount of routing resources available on the layer on which the wire jog was introduced. With this technique, tool and design intervention are needed to route the vias between the vertical and horizontal segments on the different metal layers. Thus, this technique increases the complexity of the overall semiconductor design across different layers and requires further expenditure of design time. Further, fabrication of vias is typically very expensive, and thus, this second technique usually results in higher production costs.
In view of the above, it would be desirable to have a method and/or device that permits repeaters to be easily implemented in a wire bus within pre-determined wire pitch constraints. Further, it would be desirable that the method and/or device not significantly increase the design complexity of the wire bus or integrated circuit design.
According to the principles of this invention, there are provided methods and devices for implementing repeater circuits in an integrated circuit wire bus. In one embodiment, the present invention includes a parameterized bus repeater circuit cell of variable horizontal length having a vertical width of three (3) times the wire pitch of the bus to be repeated.
The present invention can be implemented in an integrated circuit bus as separate bus repeater circuit cells, or in another embodiment, as a bus repeater circuit block having a plurality of individual bus repeater circuit cells. The embodiments of the present invention are readily adaptable to design implementations using computer-aided design tools to provide automated placement and array of the bus repeater circuit cells and bus repeater circuit blocks.
In one embodiment of the present invention, a bus repeater circuit block includes: a first signal path, having a first repeater circuit; and a second signal path adjacent the first signal path having a second repeater circuit, where the second repeater circuit is horizontally staggered with respect to the first repeater circuit.
In another embodiment of the present invention, a bus repeater circuit cell for conductive coupling to an integrated circuit bus including a plurality of individual signal wires spaced according to a pre-determined wire pitch includes: a first signal path for conductively coupling to a first signal wire, the first signal path further including a repeater circuit for amplifying a signal carried on the first signal path; a second signal path for conductive coupling to a second signal wire; and a third signal path for conductive coupling to a third signal wire, where the bus repeater circuit cell has a width three times the pre-determined wire pitch.
In a further embodiment of the present invention, a bus repeater circuit block for conductive coupling to an integrated circuit bus including a plurality of individual signal wires spaced according to a pre-determined wire pitch includes: a plurality of bus repeater circuit cells, where each of the plurality of bus repeater circuit cells has a width three times the pre-determined wire pitch, each of the plurality of bus repeater circuit cells further including: a first signal path for conductively coupling to a first signal wire, the first signal path further including a repeater circuit for amplifying a signal carried on the first signal path, the repeater circuit having a horizontal length; a second signal path for conductive coupling to a second signal wire; and a third signal path for conductive coupling to a third signal wire; where each of the repeater circuits of the plurality of bus repeater circuit cells is horizontally staggered from adjacent repeater circuits by at least the horizontal length.
As a result of these and other features discussed in more detail below, methods and devices designed according to the principles of the present invention allow repeater placement within a integrated circuit bus to be implemented without significant increases in design complexity, tool intervention, or production costs when compared to the prior art techniques earlier described.
It is to be understood that both the foregoing general description and the following detailed description are intended only to exemplify and explain the invention as claimed.